Phase locked loops (PLLs) are important components of many modern day communication circuits. During the transmission of a wireless signal, the frequency and phase of the wireless signal may become distorted resulting in differences between the transmitted carrier signal and a receiver's carrier signal. PLLs enable synchronization between the receiver's carrier signal and the transmitted carrier signal by regulating the phase and frequency of carrier signals used within a device according to a reference signal.
FIG. 1a illustrates a simplified block diagram of an exemplary phase locked loop (PLL) 100. The PLL 100 comprises a digitally controlled oscillator (DCO) 106 configured to generate a digital variable clock signal (CLKV) in the RF frequency band, which is provided to a divider chain 110 and a feedback path 112.
The divider chain 110 is configured to divide the variable clock signal CLKV to generate a plurality of output clock signals clk_out1, clk_out2, etc. within different clock domains (i.e., having different frequencies) that are provided as outputs from the PLL 100. The different output clock signals may be provided to different components of a polar modulator transmission chain, such as analog components configured to operate at a high frequency (e.g., DCO, DPA) and digital components configured to operate at lower frequencies.
The feedback path 112 comprises a time-to-digital converter (TDC) 108 configured to receive the variable clock signal CLKV and a reference signal REF. Retiming of the reference signal REF may be performed by determining a phase difference between the variable clock signal CLKV and the reference clock REF. Based upon the computed difference, adjustments are made to the output of phase detector 102. The output of the phase detector 102 is provided to a loop filter 104, which filters the output before it is received at the DCO 106. This PLL feedback loop synchronizes the variable clock signal CLKV with the reference clock REF (i.e., causing the frequency of the variable clock signal CLKV to ‘track’ the reference signal REF).
Often a delay is present between the various output clock signals of the PLL (e.g., due to the propagation and/or settling delays in various analog elements such as the DCO, dividers, quad switch, buffers, level shifters). FIG. 1b illustrates exemplary clock timing diagrams 114 associated with the PLL of FIG. 1a. In particular, FIG. 1b illustrates a reference signal REF and a variable clock signal CLKV output from DCO 106. At time T0 the variable clock signal CLKV is out of phase from the reference signal REF. However, from time T0 to time T1 the frequency of the variable clock signal is adjusted to follow the reference signal REF.
FIG. 1b also illustrates a first output clock signal clk_out1 and a second output clock signal clk_out2 generated by division of the variable clock signal CLKV. As shown in FIG. 1b, the first output clock signal clk_out1 is generated by dividing the variable clock signal CLKV by two and the second output signal clk_out2 is generated by dividing the variable clock signal CLKV by four. The clock signals exhibit a clock skew around time T2, which can be detrimental to the transmission quality of signals transmitted using polar modulation transmission chains, where close alignment between amplitude modulation (AM) and phase/frequency modulation (PM/FM) paths is required for proper operation.